As the technology that is able to encode moving image data (or moving image signals) into coded data at a low bit rate with a high compression factor and a high picture quality, various international standards, namely H.261 and H.263 standardized by the ITU (International Telecommunication Union), MPEG-1, MPEG-2, MPEG-4 standardized by the ISO (International Organization for Standardization), and VC-1 of SMPTE (Society of Motion Picture and Television Engineers) have been widely known. Recently, the ITU and the ISO have jointly standardized H.264 (see Non-Patent Document 1). Compared to the conventional moving image coding technology, H.264 is known to further improve compression efficiency and picture quality.
Recently, a high demand is raised with respect to large video screens and high-definition picture quality; hence, video images utilized in broadcasting, video content marketing and video distribution using optical disks have essentially involved high resolutions called HD (High Definition) (1920×1080 pixels, 1280×720 pixels) higher than those of conventional video images.
Complex calculations are needed in decoding moving images which are encoded according to the H.264 standard; hence, a very high calculation ability is needed to decode high-definition vide images. For this reason, decoding is not necessarily performed on the software implemented by a general-purpose processor, but decoding needs to be performed using specific semiconductor chips specified in decoding or circuit blocks called IP cores (Intellectual Property Cores). In either case, it is not a wise policy to specifically design tasks involving input/output operations with external devices, such as a task for supplying moving image bit streams to a decoding IP core and a task for managing an image buffer storing decoding results. For this reason, a cooperated operation with functionality sharing has been occasionally implemented such that these tasks are implemented using a general-purpose processor while decoding is implemented using a decoding IP core.
In the DXVA (DirectX Video Acceleration) standard used for PC (personal computer) (see Non-Patent Document 2), for example, a general-purpose processor (hereinafter, simply referred to as a CPU) implements a series of tasks for retrieving H.264 ES (Elementary Stream) from input data of MPEG-2 TS (Transport Stream), analyzing its content, and producing intermediate data according to a predetermined format. Subsequently, a decoding accelerator normally built in a GPU (Graphics Processing Unit) implements a task of decoding intermediate data and producing decoded video images. As described above, the CPU and the GPU share the functionality of decoding.
FIG. 11 is a functional block diagram of a moving image decoding device 1000 involving decoding. A bit stream storage unit 1001 such as a hard-disk unit stores bit streams of coded moving images, which are supplied to an analysis unit 1002. The analysis unit 1002 analyzes bit streams supplied thereto so as to produce intermediate data according to a predetermined format, which are then forwarded to an intermediate data storage unit 1003. Intermediate data output from the intermediate data storage unit 1003 are supplied to a decoding unit 1004. The decoding unit 1004 decodes images with reference to intermediate data and previously decoded images stored in an image memory 1005, so that the decoding result is stored in the image memory 1005. The image memory 1005 is able to store plural sections of images, to store decoded images output from the decoding unit 1004, to supply decoded images intended for subsequent decoding, and to supply images to an output unit 1006. The output unit 1006 outputs images input thereto so as to display images. A control unit 1007 involves controls as to which section among sections of the image memory 1005 needs to be supplied for decoding of the decoding unit 1004, which section the decoding result needs to be stored in, and which section needs to be supplied to the output unit 1006. Additionally, the control unit 1007 controls the analysis unit 1002, the decoding unit 1004, and the output unit 1006, thus implementing decoding.
Various options are provided on the functionality sharing between the CPU and the GPU. FIGS. 12 and 13 show examples of the functionality sharing between the CPU and the GPU with the moving image decoding device 1000 shown in FIG. 11. In the moving image decoding device shown in FIG. 12, for example, the function of the decoding unit 1004 is solely assigned to the GPU, whilst the other functions are all assigned to the CPU and the storage unit connected to the CPU.
In the moving image decoding device shown in FIG. 13, the functions of the decoding unit 1004, the image memory 1005 and the output unit 1006 are assigned to the GPU and the storage unit connected to the GPU, whilst the other functions are assigned to the CPU and the storage unit connected to the CPU.
A plurality of modes is determined with respect to the format of intermediate data stored in the intermediate data storage unit 1003. For instance, information regarding SPS (Sequence Parameter Set), PPS (Picture Parameter Set) and Slice Header is analyzed by the CPU so that the analysis result is supplied to the CPU, whilst information of Slice Data is not analyzed by the CPU so that bit streams are directly supplied to the GPU.
FIG. 14 shows an exemplary configuration of intermediate data. The intermediate data includes header analysis information 2002, image buffer information 2003, and a bit stream 2004. The analysis unit 1002 analyzes bit streams of SPS, PPS and Slice Header, so that the analysis result is stored as the head analysis information 2003. For instance, the header analysis information 2003 includes information regarding widths and heights of images, num_ref_frames regarding the number of reference pictures used for decoding, FieldOrderCnt regarding the order of outputting pictures, and pic_init_qp_minus26 regarding an initial value of a quantization parameter used for decoding pictures.
The image buffer information 2003 includes information regarding the status of DPB (Decoded Picture Buffer) used for decoding. With the DPB operations, such as adding pictures to the DPB, eliminating pictures from the DPB, and changing the status of reference in the DPB, the status of the DPB, at a time of decoding a specific picture when the analysis unit 1002 processes bit streams according to analysis information regarding SPS, PSP, is stored as the image buffer information 2003. The image buffer information 2003 includes FieldOrderCnt for each reference frame, FrameNum, and a flag as to whether or not to denote Long Term reference picture. Since the entity of image data is stored in the image memory 1005 of the moving image decoding device shown in FIG. 11, index information (i.e. an image-memory index) indicating the correspondence between each picture of the DPB and the section of image data within the image memory 1005, is also stored in the image buffer information 2003. The analysis unit 1002 analyzes bit streams so as to retrieve a bit stream of Slice Date, which is then stored in the bit stream 2004.